ENICSF2811PBKA datasheet(132/172 Pages) TI1

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DIN

d(XCOHL-XRDL)

d(XCOH-XA)

d(XCOH-XZCSL)

d(XCOHL-XRDH)

h(XD)XRD

d(XCOHL-XZCSH)

XCLKOUT = XTIMCLK

XCLKOUT = 1/2 XTIMCLK

XZCS0AND1 XZCS2

XZCS6AND7

XA[0:18]

XRD

XWE

XR/W

XD[0:15]

su(XD)XRD

a(A)

a(XRD)

XREADY

Lead

Active

Trail

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174T – APRIL 2001 – REVISED MAY 2012

www.ti.com

All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an

alignment cycle before an access to meet this requirement.

During alignment cycles, all signals will transition to their inactive state.

For USEREADY = 0, the external XREADY input signal is ignored.

XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.

Figure 6-31. Example Read Access

XTIMING register parameters used for this example:

XRDLEAD

XRDACTIVE

XRDTRAIL

USEREADY

X2TIMING

XWRLEAD

XWRACTIVE

XWRTRAIL

READYMODE

≥ 1

≥ 0

N/A(1)

(1)

N/A = “Don’t care” for this example

132

Electrical Specifications

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

ENICSF2811PBKA 数据表(PDF) 132 Page - Texas Instruments

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