ENICSF2811PBKA datasheet(131/172 Pages) TI1

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TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

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SPRS174T – APRIL 2001 – REVISED MAY 2012

6.24 External Interface Read Timing

Table 6-32. External Memory Interface Read Switching Characteristics

PARAMETER

MIN

MAX

UNIT

td(XCOH-XZCSL)

Delay time, XCLKOUT high to zone chip-select active-low

td(XCOHL-XZCSH)

Delay time, XCLKOUT high/low to zone chip-select inactive-high

–2

td(XCOH-XA)

Delay time, XCLKOUT high to address valid

td(XCOHL-XRDL)

Delay time, XCLKOUT high/low to XRD active-low

td(XCOHL-XRDH)

Delay time, XCLKOUT high/low to XRD inactive-high

–2

th(XA)XZCSH

Hold time, address valid after zone chip-select inactive-high

(1)

th(XA)XRD

Hold time, address valid after XRD inactive-high

(1)

During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

Table 6-33. External Memory Interface Read Timing Requirements

MIN

MAX

UNIT

ta(A)

Access time, read data from address valid

(LR + AR) – 14(1)

ta(XRD)

Access time, read data valid from XRD active-low

AR – 12(1)

tsu(XD)XRD

Setup time, read data valid before XRD strobe inactive-high

th(XD)XRD

Hold time, read data valid after XRD inactive-high

(1)

LR = Lead period, read access. AR = Active period, read access. See Table 6-30.

Electrical Specifications

131

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