ENICSF2811PBKA datasheet(140/172 Pages) TI1

140 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174T – APRIL 2001 – REVISED MAY 2012

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6.28 XHOLD and XHOLDA

If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the

XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of

high-impedance mode.

On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the

bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active

low.

When HOLD mode is enabled and XHOLDA is active-low (external bus grant active), the CPU can still

execute code from internal memory. If an access is made to the external interface, the CPU is stalled until

the XHOLD signal is removed.

An external DMA request, when granted, places the following signals in a high-impedance mode:

XA[18:0]

XZCS0AND1

XD[15:0]

XZCS2

XWE, XRD

XZCS6AND7

XR/W

All other signals not listed in this group remain in their default or functional operational modes during these

signal events.

140

Electrical Specifications

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ENICSF2811PBKA 数据表(PDF) 140 Page - Texas Instruments