ENICSF2811PBKA datasheet(141/172 Pages) TI1

141 / 172 page

XCLKOUT

(/1 Mode)

XHOLD

XR/

XZCS0AND1

XZCS2

XZCS6AND7

XD[15:0]

Valid

XHOLDA

d(HL-Hiz)

d(HH-HAH)

High-Impedance

XA[18:0]

Valid

High-Impedance

d(HH-BV)

d(HL-HAL)

See Note (A)

See Note (B)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

6.29 XHOLD/XHOLDA Timing

Table 6-42. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)(1)(2)

MIN

MAX

UNIT

td(HL-HiZ)

Delay time, XHOLD low to Hi-Z on all Address, Data, and Control

4tc(XTIM)

td(HL-HAL)

Delay time, XHOLD low to XHOLDA low

5tc(XTIM)

td(HH-HAH)

Delay time, XHOLD high to XHOLDA high

3tc(XTIM)

td(HH-BV)

Delay time, XHOLD high to Bus valid

4tc(XTIM)

(1)

When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance

state.

(2)

The state of XHOLD is latched on the rising edge of XTIMCLK.

All pending XINTF accesses are completed.

Normal XINTF operation resumes.

Figure 6-37. External Interface Hold Waveform

Electrical Specifications

141

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

ENICSF2811PBKA 数据表(PDF) 141 Page - Texas Instruments

ENICSF2811PBKA 数据表(HTML) 141 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载