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TNETV2685FIBZUT9 数据表(PDF) 112 Page - Texas Instruments |
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TNETV2685FIBZUT9 数据表(HTML) 112 Page - Texas Instruments |
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112 / 191 page  AECLKIN 2 3 4 4 5 1 TMS320DM647 TMS320DM648 SPRS372H – MAY 2007 – REVISED APRIL 2012 www.ti.com Table 6-41. EMIFA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x7000 00A4 - 0x7000 00BC - Reserved 0x7000 00C0 INTRAW EMIFA Interrupt RAW Register 0x7000 00C4 INTMSK EMIFA Interrupt Masked Register 0x7000 00C8 INTMSKSET EMIFA Interrupt Mask Set Register 0x7000 00CC INTMSKCLR EMIFA Interrupt Mask Clear Register 0x7000 00D0 - 0x7000 00DC - Reserved 0x7000 00E0 - 0x77FF FFFF - Reserved 6.10.3 EMIFA Electrical Data/Timing Table 6-42. Timing Requirements for AECLKIN for EMIFA(1) (2) (see Figure 6-19) 720, 800, 900, 1100 NO. UNIT MIN MAX 1 tc(EKI) Cycle time, AECLKIN 6(3) 16P(4) ns 2 tw(EKIH) Pulse duration, AECLKIN high 2.7 ns 3 tw(EKIL) Pulse duration, AECLKIN low 2.7 ns 4 tt(EKI) Transition time, AECLKIN 2 ns 5 tJ(EKI) Period Jitter, AECLKIN 0.02E(5) ns (1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. (2) E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA. (3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. (4) P is P = 1/CPU clock frequency in ns. (5) This timing applies only when AECLKIN is used for EMIFA. Figure 6-19. AECLKIN Timing for EMIFA Table 6-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module(1) (2) (3) (see Figure 6-20) 720, 800, 900, 1100 NO. PARAMETER UNIT MIN MAX 1 tc(EKO) Cycle time, AECLKOUT E - 0.7 E + 0.7 ns 2 tw(EKOH) Pulse duration, AECLKOUT high EH - 0.7 EH + 0.7 ns 3 tw(EKOL) Pulse duration, AECLKOUT low EL - 0.7 EL + 0.7 ns 4 tt(EKO) Transition time, AECLKOUT 1 ns 5 td(EKIH-EKOH) Delay time, AECLKIN high to AECLKOUT high 1 8 ns 6 td(EKIL-EKOL) Delay time, AECLKIN low to AECLKOUT low 1 8 ns (1) E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA. (2) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. (3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA. 112 Peripheral Information and Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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