ST7FOXU0 datasheet(76/123 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7FOXU0

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Bits 15:12 = Reserved, must be kept cleared.

Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value

This 12-bit value is written by software. The high register must be written first.

In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty

cycle of the PWM0 output signal (see Figure 33). In Output Compare mode, (OE0=0 in

the PWMCR register) they define the value to be compared with the 12-bit upcounter

value.

PWM0 control/status register (PWM0CSR)

Reset value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = OP0 PWM0 Output Polarity.

This bit is read/write by software and cleared by hardware after a reset. This bit selects

the polarity of the PWM0 signal.

0: The PWM0 signal is not inverted.

1: The PWM0 signal is inverted.

Bit 0 = CMPF0 PWM0 Compare Flag.

This bit is set by hardware and cleared by software by reading the PWM0CSR register.

It indicates that the upcounter value matches the DCR0 register value.

0: Upcounter value does not match DCR value.

1: Upcounter value matches DCR value.

PWM output control register (PWMCR)

Reset value: 0000 0000 (00h)

Bits 7:1 = Reserved, must be kept cleared.

Bit 0 = OE0 PWM0 Output enable.

OP0

CMPF0

Read/Write

OE0

Read/Write

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