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ST7FOXU0 数据表(PDF) 33 Page - STMicroelectronics |
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ST7FOXU0 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 123 page ![]() ST7FOXU0 Supply, reset and clock management 33/123 6.3.5 Internal watchdog reset The Reset sequence generated by an internal watchdog counter overflow is shown in Figure 13: Reset sequences Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 13. Reset sequences tw(RSTL)out RUN RUN WATCHDOG RESET INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH ACTIVE PHASE VDD RUN RESET PIN EXTERNAL WATCHDOG ACTIVE PHASE VIT+(LVD) VIT-(LVD) th(RSTL)in RUN WATCHDOG UNDERFLOW RESET RESET SOURCE EXTERNAL RESET LVD RESET ACTIVE PHASE |
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