ST7FOXU0 datasheet(23/123 Pages) STMICROELECTRONICS

23 / 123 page

ST7FOXU0

Central processing unit

23/123

Bit 3 = I Interrupt mask bit

This bit is set by hardware when entering in interrupt or by software to disable all

interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM

and JRNM instructions.

Note:

Interrupts requested while I is set are latched and can be processed when I is cleared. By

default an interrupt routine is not interruptible because the I bit is set by hardware at the start

of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared

by software in the interrupt routine, pending interrupts are serviced regardless of the priority

level of the current interrupt routine.

Bit 2 = N Negative bit

This bit is set and cleared by hardware. It is representative of the result sign of the last

arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative (that is, the most significant bit is a logic

1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero bit

This bit is set and cleared by hardware. This bit indicates that the result of the last

arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow bit

This bit is set and cleared by hardware and software. It indicates an overflow or an

underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

5.3.5

Stack Pointer (SP)

Reset value: 00FFh

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the

stack. It is then decremented after data has been pushed onto the stack and incremented

before data is popped from the stack (see Figure 6).

SP5 SP4 SP3 SP2 SP1 SP0

Read/write

ST7FOXU0 数据表(PDF) 23 Page - STMicroelectronics

ST7FOXU0 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载