ST7FOXU0 datasheet(40/123 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST7FOXU0

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6.5.5

Prescaler register (PSCR)

Reset value: 0000 0011 (03h)

Bits 7:5 = CK[2:0] internal RC Prescaler Selection

These bits are set by software and cleared by hardware after a reset. These bits select

the prescaler of the internal RC oscillator. See Figure 10: ST7FOXU0 clock

management block diagram on page 29 and Table 8.

If the internal RC is used with a supply operating range below 3.3 V, a division ratio of

at least 2 must be enabled in the RC prescaler.

Bits 4:0 = Reserved, must be kept at their reset value.

6.5.6

Clock controller control/status register (CKCNTCSR)

Reset value: 0000 1001 (09h)

Bits 7:4 = Reserved, must be kept cleared.

Bit 3 = AWU_FLAG AWU Selection bit

This bit is set and cleared by hardware.

0: No switch from AWU to RC requested

1: AWU clock activated and temporization completed

Bit 2 = RC_FLAG RC Selection bit

This bit is set and cleared by hardware.

0: No switch from RC to AWU requested

1: RC clock activated and temporization completed

Bit 1 = Reserved, must be kept cleared.

CK2

CK1

CK0

Read/write

Table 8.

Internal RC prescaler selection bits

CK2

CK1

CK0

fOSC

fRC/2

fRC/4

fRC/8

fRC/16

others

fRC

AWU_FLAG

RC_FLAG

RC/AWU

Read/write

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