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数据搜索系统，热门电子元器件搜索 |
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ST7FOXU0 数据表(PDF) 39 Page - STMicroelectronics |
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ST7FOXU0 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 123 page  ST7FOXU0 Supply, reset and clock management 39/123 6.5.4 RC Control Register Low (RCCRL) Reset value: 0000 0000 (00h) Bit 7 = Reserved, must be kept cleared Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately after reset to adjust the RC oscillator frequency. Refer to Section 6.1.1: Internal RC oscillator on page 25. Bits 4:3 = Reserved, must be kept cleared Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled by option byte, the LVDRF bit value is undefined. The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not. Bits 1:0 = Reserved, must be kept cleared 7 0 0 CR1 CR0 0 0 LVDRF 0 0 Read/write |
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