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STM8S005C6 数据表(PDF) 11 Page - STMicroelectronics |
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STM8S005C6 数据表(HTML) 11 Page - STMicroelectronics |
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11 / 97 page  DocID022186 Rev 4 11/97 STM8S005C6 STM8S005K6 Block diagram 25 3 Block diagram Figure 1. STM8S005C6/K6 value line block diagram XTAL 1-16 MHz RC int. 16 MHz RC int. 128 kHz STM8 core Debug/SWIM UART2 I2C SPI AWU timer Reset block Reset POR BOR Clock controller Detector Clock to peripherals and core 400 Kbit/s 8 Mbit/s up to 10 Window WDG 32 Kbytes high 128 bytes 2 Kbytes RAM Boot ROM ADC1 Reset Single wire debug interf. density program Flash data EEPROM 16-bit general purpose 16-bit advanced control timer (TIM1) timers (TIM2, TIM3) 8-bit basic timer (TIM4) Beeper 1/2/4 kHz beep Independent WDG 4 CAPCOM channels Up to 5 CAPCOM channels Up to + 3 complementary outputs Master/slave autosynchro LIN master SPI emul. channels |
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