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STM8S005C6 数据表(PDF) 34 Page - STMicroelectronics |
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STM8S005C6 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 97 page  Memory and register map STM8S005C6 STM8S005K6 34/97 DocID022186 Rev 4 0x00 532B TIM3 TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 0x00 5331 to 0x00 533F Reserved area (15 bytes) 0x00 5340 TIM4 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF 0x00 5347 to 0x00 53FF Reserved area (185 bytes) 0x00 5400 ADC1 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 0x00 5408 ADC_HTRH ADC high threshold register high 0x03 0x00 5409 ADC_HTRL ADC high threshold register low 0xFF 0x00 540A ADC_LTRH ADC low threshold register high 0x00 0x00 540B ADC_LTRL ADC low threshold register low 0x00 0x00 540C ADC_AWSRH ADC analog watchdog status register high 0x00 0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00 0x00 540E ADC_AWCRH ADC analog watchdog control register high 0x00 0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00 0x00 5410 to 0x00 57FF Reserved area (1008 bytes) Table 8. General hardware register map (continued) Address Block Register label Register name Reset status |
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