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STM8S005C6 数据表(PDF) 47 Page - STMicroelectronics |
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STM8S005C6 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 97 page  DocID022186 Rev 4 47/97 STM8S005C6 STM8S005K6 Electrical characteristics 84 Figure 9. fCPUmax versus VDD Table 18. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2(1) 1. Guaranteed by design, not tested in production. - µs/V VDD fall time rate - 2(1) - tTEMP Reset release delay VDD rising - - 1.7(1) ms VIT+ Power-on reset threshold(2) 2. If VDD is below 2.95 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is kept. The EEPROM programming sequence must not be initiated. - 2.65 2.8 2.95 V VIT- Brown-out reset threshold - 2.58 2.73 2.88 V VHYS(BOR) Brown-out reset hysteresis -- 70 - mV |
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