STM8S005C6 datasheet(38/97 Pages) STMICROELECTRONICS

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Option bytes

STM8S005C6 STM8S005K6

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DocID022186 Rev 4

Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated block of the memory. Except for the

ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form

(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in Table 11: Option bytes below. Option bytes can also be modified ‘on the fly’ by the

application in IAP mode, except the ROP option that can only be modified in ICP mode (via

SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM

communication protocol and debug module user manual (UM0470) for information on SWIM

programming procedures.

Table 11. Option bytes

Addr.

Option

name

Option

byte no.

Option bits

Factory

default

setting

321

4800h

Read-out

protection

(ROP)

OPT0

ROP[7:0]

00h

4801h

User boot code

(UBC)

OPT1

UBC[7:0]

00h

4802h

NOPT1

NUBC[7:0]

FFh

4803h

Alternate

function

remapping

(AFR)

OPT2

AFR7

AFR6

AFR5

Reserve

AFR3

AFR2

AFR1

AFR0

00h

4804h

NOPT2

NAFR7

NAFR6

NAFR5

NAFR4

NAFR3

NAFR2

NAFR1

NAFR0

FFh

4805h

Miscellaneous

option

OPT3

Reserved

HSITRIM

LSI

_EN

IWDG

_HW

WWDG

_HW

WWDG

_HALT

00h

4806h

NOPT3

Reserved

NHSI

TRIM

NLSI

_EN

NIWDG

_HW

NWWDG

_HW

NWWDG

_HALT

FFh

4807h

Clock option

OPT4

Reserved

EXT

CLK

CKAWU

SEL

PRS

00h

4808h

NOPT4

Reserved

CLK

NCKAW

USEL

NPR

SC1

NPR

SC0

FFh

4809h

HSE clock

startup

OPT5

HSECNT[7:0]

00h

480Ah

NOPT5

NHSECNT[7:0]

FFh

480Bh

Reserved

OPT6

Reserved

00h

480Ch

NOPT6

Reserved

FFh

480Dh

Flash wait

states

OPT7

Reserved

00h

480Eh

NOPT7

Reserved

FFh

487Eh

Bootloader

OPTBL

BL[7:0]

00h

487Fh

NOPTBL

NBL[7:0]

FFh

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