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STM32F769AI 数据表(PDF) 174 Page - STMicroelectronics |
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STM32F769AI 数据表(HTML) 174 Page - STMicroelectronics |
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174 / 255 page  Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 174/255 DocID029041 Rev 4 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 43 or Figure 44, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176 and TFBGA216. When VREF- is not available, it isinternally connected to VDDA and VSSA. Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176 and TFBGA216. When VREF- is not available, it isinternally connected to VDDA and VSSA. |
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