STM32F769AI datasheet(177/255 Pages) STMICROELECTRONICS

177 / 255 page

DocID029041 Rev 4

177/255

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Electrical characteristics

224

IDDA(4)

DAC DC VDDA current

consumption in quiescent

mode(3)

280

380

μA

With no load, middle code (0x800) on the

inputs

475

625

μA

With no load, worst code (0xF1C) at

VREF+ = 3.6 V in terms of DC

consumption on the inputs

DNL(4)

Differential non linearity

Difference between two

consecutive code-1LSB)

±0.5

LSB Given for the DAC in 10-bit configuration.

±2

LSB Given for the DAC in 12-bit configuration.

INL(4)

Integral non linearity

(difference between

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 1023)

±1

LSB Given for the DAC in 10-bit configuration.

±4

LSB Given for the DAC in 12-bit configuration.

Offset(4)

Offset error

(difference between

measured value at Code

(0x800) and the ideal value =

VREF+/2)

±10

mV Given for the DAC in 12-bit configuration

±3

LSB

Given for the DAC in 10-bit at VREF+ =

3.6 V

±12

LSB

Given for the DAC in 12-bit at VREF+ =

3.6 V

Gain

error(4)

Gain error

±0.5

Given for the DAC in 12-bit configuration

tSETTLING(4)

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±4LSB

-3

μs

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

THD(4)

Total Harmonic Distortion

Buffer ON

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

Update

rate(2)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

MS/s

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

tWAKEUP(4)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

μs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest and highest

possible ones.

PSRR+ (2)

Power supply rejection ratio

(to VDDA) (static DC

measurement)

–67

–40

dB No RLOAD, CLOAD = 50 pF

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2:

Internal reset OFF).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed by characterization results.

Table 82. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

STM32F769AI 数据表(PDF) 177 Page - STMicroelectronics

STM32F769AI 数据表(HTML) 177 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

STM32F769AI 数据表(PDF) 177 Page - STMicroelectronics

STM32F769AI 数据表(HTML) 177 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载