STM32F769AI datasheet(181/255 Pages) STMICROELECTRONICS

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DocID029041 Rev 4

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Electrical characteristics

224

Figure 46. SPI timing diagram - slave mode and CPHA = 0

tsu(MI)

Data input setup time

Master mode

9(4)

tsu(SI)

Slave mode

4.5

th(MI)

Data input hold time

Master mode

0(4)

th(SI)

Slave mode

ta(SO)

Data output access time

Slave mode

tdis(SO)

Data output disable time

Slave mode

tv(SO)

Data output valid time

Slave mode 2.7≤VDD≤3.6V

6.5

Slave mode 1.71≤VDD≤3.6V

6.5

13.5

tv(MO)

Master mode

th(SO)

Data output hold time

Slave mode

1.71≤VDD≤3.6V

4.5

th(MO)

Master mode

1. Guaranteed by characterization results.

2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz.

3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK

level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having

Tsu(MI)=0 while signal Duty(SCK)=50%.

4. Only for SPI6.

Table 85. SPI dynamic characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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