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STM32F769AI 数据表(PDF) 191 Page - STMicroelectronics

部件名 STM32F769AI
功能描述  Dual mode Quad-SPI
PDF  255 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F769AI 数据表(HTML) 191 Page - STMicroelectronics

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
Electrical characteristics
224
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 95 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 94
and VDD supply voltage conditions summarized in Table 93, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
Capacitive load C = 20 pF, unless otherwise specified
Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 5.3.20: I/O port characteristics for more details on the input/output
characteristics.
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
Table 93. USB HS DC electrical characteristics
Symbol
Parameter
Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1)
Unit
Input level
VDD
USB OTG HS operating voltage
1.7
3.6
V
Table 94. USB HS clock timing parameters(1)
1. Guaranteed by design.
Symbol
Parameter
Min
Typ
Max
Unit
-
fHCLK value to guarantee proper operation of
USB HS interface
30
-
-
MHz
FSTART_8BIT
Frequency (first transition)
8-bit ±10%
54
60
66
MHz
FSTEADY
Frequency (steady state) ±500 ppm
59.97
60
60.03
MHz
DSTART_8BIT
Duty cycle (first transition)
8-bit ±10%
40
50
60
%
DSTEADY
Duty cycle (steady state) ±500 ppm
49.975
50
50.025
%
tSTEADY
Time to reach the steady state frequency and
duty cycle after the first transition
-
-
1.4
ms
tSTART_DEV
Clock startup time after the
de-assertion of SuspendM
Peripheral
-
-
5.6
ms
tSTART_HOST
Host
-
-
-
tPREP
PHY preparation time after the first transition
of the input clock
--
-
μs



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