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STA339BWS 数据表(PDF) 59 Page - STMicroelectronics |
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STA339BWS 数据表(HTML) 59 Page - STMicroelectronics |
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59 / 79 page ![]() DocID015276 Rev 8 59/79 STA339BWS Register description 79 7.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) 7.7.7 Coefficient read/write control register (addr 0x26) 7.7.8 Description Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA339BWS via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM. Three different RAM banks are embedded in STA339BWS. The three banks are managed in paging mode using EQCFG register bits. They can be used to store different EQ settings. For speaker frequency compensation, a sampling frequency independent EQ must be implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and downloading them into the three RAM banks, it is possible to select the suitable RAM block depending from the incoming frequency with a simple I2C write operation on register 0x31. For example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at the start up, and during the normal play it is possible to switch among the three RAM blocks allowing a faster operation, without any additional download from the microcontroller. To write the coefficients in a particular RAM bank, this bank must be selected first writing bit 0 and bit 1 in register 0x31. Then the write procedure below can be used. Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to the coefficients stored in the active RAM block. Note: The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and stable (ref. Table 8, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D). D7 D6 D5 D4 D3 D2 D1 D0 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 00000000 D7 D6 D5 D4 D3 D2 D1 D0 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 00000000 D7 D6 D5 D4 D3 D2 D1 D0 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0 00000000 D7 D6 D5 D4 D3 D2 D1 D0 Reserved RA R1 WA W1 0 0 000 |
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