STA339BWS datasheet(50/79 Pages) STMICROELECTRONICS

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STA339BWS

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DocID015276 Rev 8

Binary output enable registers

Each individual channel output can be set to output a binary PWM stream. In this mode

output A of a channel is considered the positive output and output B is negative inverse.

Limiter select

Limiter selection can be made on a per-channel basis according to the channel limiter select

bits. CxLS bits are not considered when dual band DRC (Section 7.13.1 on page 67) or

EQ DRC (Section 7.13.2) is used.

Output mapping

Output mapping can be performed on a per channel basis according to the CxOM channel

output mapping bits. Each input into the output configuration engine can receive data from

any of the three processing channel outputs.

Table 62. Binary output enable registers

CxBO

Mode

FFX output operation

Binary output

Table 63. Channel limiter mapping as a function of CxLS bits

CxLS[1:0]

Channel limiter mapping

Channel has limiting disabled

Channel is mapped to limiter #1

Channel is mapped to limiter #2

Table 64. Channel output mapping as a function of CxOM bits

CxOM[1:0]

Channel x output source from

Channel1

Channel 2

Channel 3

STA339BWS 数据表(PDF) 50 Page - STMicroelectronics