STA339BWS datasheet(45/79 Pages) STMICROELECTRONICS

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STA339BWS

7.2.1

Mute/line output configuration register (addr 0x06)

Line output is only active when OCFG = 00. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

7.2.2

Master volume register (addr 0x07)

7.2.3

Channel 1 volume (addr 0x08)

7.2.4

Channel 2 volume (addr 0x09)

LOC1

LOC0

Reserved

C3M

C2M

C1M

Reserved

00010000

Table 51. Line output configuration

LOC[1:0]

Line output configuration

Line output fixed - no volume, no EQ

Line output variable - channel 3 volume effects line output, no EQ

Line output variable with EQ - channel 3 volume effects line output

MVOL7

MVOL6

MVOL5

MVOL4

MVOL3

MVOL2

MVOL1

MVOL0

11111111

Table 52. Master volume offset as a function of MVOL[7:0]

MVOL[7:0]

Volume offset from channel value

00000000 (0x00)

0 dB

00000001 (0x01)

-0.5 dB

00000010 (0x02)

-1 dB

……

01001100 (0x4C)

-38 dB

……

11111110 (0xFE)

-127.5 dB

11111111 (0xFF)

Default mute, not to be used during operation

C1VOL7

C1VOL6

C1VOL5

C1VOL4

C1VOL3

C1VOL2

C1VOL1

C1VOL0

01100000

C2VOL7

C2VOL6

C2VOL5

C2VOL4

C2VOL3

C2VOL2

C2VOL1

C2VOL0

01100000

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