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STA339BWS 数据表(PDF) 16 Page - STMicroelectronics |
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STA339BWS 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 79 page  Electrical specifications STA339BWS 16/79 DocID015276 Rev 8 3.6 Power on/off sequence Figure 4. Power-on sequence Note: The definition of a stable clock is when fmax - fmin < 1 MHz. Section Serial audio input interface format on page 27 gives information on setting up the I2S interface. Figure 5. Power-off sequence for pop-free turn-off Note: no specific VCC and VDD_DIG turn −on sequence is required TR = minimum time between XTI master clock stable and Reset removal: 1 ms TC = minimum time between Reset removal and I2C program, sequence start: 1ms Note: no specific VCC and VDD_DIG turn −off sequence is required |
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