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STA339BWS 数据表(PDF) 30 Page - STMicroelectronics

部件名 STA339BWS
功能描述  FFX with 100-dB SNR and dynamic range
PDF  79 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA339BWS 数据表(HTML) 30 Page - STMicroelectronics

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Register description
STA339BWS
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DocID015276 Rev 8
Channel input mapping
Each channel received via I2S can be mapped to any internal processing channel via the
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers maps each I2S input channel to its corresponding processing
channel.
7.1.3
Configuration register C (addr 0x02)
FFX power output mode
The FFX power output mode selects how the FFX output timing is configured.
Different power devices use different output modes.
FFX compensating pulse size register
Table 22. Channel input mapping
Bit
R/W
RST
Name
Description
6
R/W
0
C1IM
0: processing channel 1 receives left I2S Input
1: processing channel 1 receives right I2S Input
7
R/W
1
C2IM
0: processing channel 2 receives left I2S Input
1: processing channel 2 receives right I2S Input
D7
D6
D5
D4
D3
D2
D1
D0
OCRB
Reserved
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
10010111
Table 23. FFX power output mode
Bit
R/W
RST
Name
Description
0
R/W
1
OM0
Selects configuration of FFX output:
00: drop compensation
01: discrete output stage: tapered compensation
10: full-power mode
11: variable drop compensation (CSZx bits)
1
R/W
1
OM1
Table 24. FFX compensating pulse size bits
Bit
R/W
RST
Name
Description
2
R/W
1
CSZ0
When OM[1,0] = 11, this register determines the size
of the FFX compensating pulse from 0 clock ticks to
15 clock periods.
3
R/W
1
CSZ1
4
R/W
1
CSZ2
5
R/W
0
CSZ3



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