TAS3001CPWR datasheet(15/56 Pages) TI

15 / 56 page

2−1

2 Audio Data Formats

2.1

Serial Audio Interface

The TAS3001 operates in digital audio slave mode only. The TAS3001 supports three serial audio data formats: I2S,

left-justified, and right-justified. Data word lengths of 16, 18, and 20 bits are supported.

Data is input into SDIN1 and SDIN2 under the influence of the master clock (MCLK), left/right clock (LRCLK), and

shift clock (SCLK) inputs.

Data is output on the SDOUT pin under the influence of the master clock (MCLK) input plus the left/right clock

(LRCLKOUT) and shift clock (SCLKOUT) outputs. LRCLKOUT and SCLKOUT are generated from the MCLK input

(usually at 256

× fs). Typically these are routed on the PCB to LRCLK (as the input fs sample clock) and SCLK (as

the input 64

× fs bit clock).

The TAS3001 device is compatible with 10 different serial interfaces. Available interface options are I2S,

right-justified, and left-justified. Table 2−1 and Table 2−2 indicate how the 10 options are selected using the I2C bus

and the main control register (MCR, I2C address 01h). All serial interface options at either 16, 18, or 20 bits operate

with SCLK at 64

× fs. The 16-bit mode, left-justified, can operate at 32 × fs or 64 × fs.

Table 2−1. Serial Interface Input Options

MODE

MCR BIT 6

MCR BITS 3−2

F(1,0)

MCR BITS 1−0

W(1,0)

SERIAL INTERFACE

SDIN1, SDIN2

16-bit, left-justified, 32

× fs

16-bit, left-justified, 64

× fs

16-bit, right-justified, 64

× fs

16-bit, I2S, 64

× fs

18-bit, left-justified, 64

× fs

18-bit, right-justified, 64

× fs

18-bit, I2S, 64

× fs

20-bit, left-justified, 64

× fs

20-bit, right-justified, 64

× fs

20-bit, I2S, 64

× fs

Table 2−2. Serial Interface Output Options

MODE

MCR BIT 6

MCR BITS 5−4

E(1,0)

MCR BITS 1−0

W(1,0)

SERIAL INTERFACE

SDOUT

16-bit, left-justified, 32

× fs

16-bit, left-justified, 64

× fs

16-bit, right-justified, 64

× fs

16-bit, I2S, 64

× fs

18-bit, left-justified, 64

× fs

18-bit, right-justified, 64

× fs

18-bit, I2S, 64

× fs

20-bit, left-justified, 64

× fs

20-bit, right-justified, 64

× fs

20-bit, I2S, 64

× fs

Figure 2−1 through Figure 2−4 illustrate the relationship between the SCLK, LRCLK, and the serial data input and

output protocol options.

TAS3001CPWR 数据表(PDF) 15 Page - Texas Instruments

TAS3001CPWR 数据表(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载

链接网址

TAS3001CPWR 数据表(PDF) 15 Page - Texas Instruments

TAS3001CPWR 数据表(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表 下载

链接网址

数据表下载