TAS3001CPWR datasheet(21/56 Pages) TI

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3−1

3 Serial Control Interface (I2C)

The TAS3001 operation is controlled using the RESET signal and the serial control interface. Control information is

downloaded into the TAS3001 control registers by an I2C master device, such as a microprocessor, microcontroller,

or DSP. These registers control the settings for volume, bass, treble, mixing, and filtering. A description of the register

addresses and control formats is given in Appendix A.

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Each device is addressed by sending a unique 7-bit slave address plus an R/W bit (1 byte).

All I2C compatible devices are controlled using the SDA and SCL signals using a wire-ANDed connection. A pullup

resistor must be used to set the high level on the bus. The TAS3001 operates in standard I2C mode up to 100 kbps

with as many devices on the bus as desired up to the capacitance load limit of 400 pF.

The TAS3001 is an I2C slave-only device; therefore, at least one device connected to the I2C bus with this device

must operate in master mode. The pullup resistor is generally 4.99 k

Ω. Upon power up, the I2C is in an unknown state

until the master clock has been applied and the TAS3001 has been reset. Prior to reset, the TAS3001 may hold the

SDA and/or SCL lines low. This creates I2C communication errors for any other device that attempts to use the bus.

3.1

I2C Protocol

The bus standard uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions.

A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit

transitions must occur within the low time of the clock period. These conditions are shown in Figure 3−1. These start

and stop conditions for the I2C bus are required by standard protocol to be generated by the master. The master must

also generate the 7-bit slave address and the read/write (R/W) bit to open communication with another device and

then wait for an acknowledge condition. The slave holds SDA low during acknowledge clock period to indicate an

acknowledgment. When this occurs, the master transmits the next byte of the sequence.

After each 8-bit word, an acknowledgment must be transmitted by the receiving device. There is no limit on the

number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master

generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 3−1. Definitions

for the I2C protocol terms are listed in Table 3−1.

7 Bit Slave Address

R/W

8 Bit Subaddress (N)

8 Bit Data For

Address (N)

8 Bit Data For

Address (N)

543

Start

Stop

SDA

SCL

Figure 3−1. Typical I2C Data Transfer Sequence

Table 3−1. I2C Protocol Definitions

DEFINITION

DESCRIPTION

Master

The device that initiates a transfer, generates clock signals, and terminates the transfer

Receiver

The device that receives data

Slave

The device addressed by the master

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