TAS3001CPWR datasheet(22/56 Pages) TI

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3−2

3.2

Operation

To permit multiple devices to be controlled via the I2C bus, each slave device has an address. The TAS3001 has been

assigned four unique addresses to permit multiple TAS3001s to be used in a system. The addresses are selected

using the CS1 and CS2 pins. These four addresses, listed in Table 3−2, are licensed I2C addresses and do not conflict

with other licensed I2C audio devices. To communicate with the TAS3001, the I2C master must use the address

01101XX. In addition to the 7-bit device address, subaddresses are used to direct communication to the proper

memory location within the device. A complete table of subaddresses and control registers is provided in Appendix A,

Software Interface.

Table 3−2. TAS3001 I2C Address

I2C ADDRESS BYTE

A6−A2

CS2(A1)

CS1(A0)

R/W

68h

01101

6Ah

01101

6Ch

01101

6Eh

01101

3.2.1

Write Cycle Example

An example write cycle is demonstrated in Figure 3−2 and Table 3−3.

Start

Slave Address

R/W

Subaddress

Data Byte 1

Data Byte 2

Data Byte N

Stop

Figure 3−2. Write Cycle Example

Table 3−3. Write Cycle Example

FUNCTION

DESCRIPTION

Start

Start condition as defined in I2C

Slave address

0110100 (CS1 = CS2 = 0)

R/W

0 (write)

Acknowledgement as defined in I2C (slave)

Subaddress

00000110 (see Appendix A, Software Interface)

Data

00011100 (see Appendix A, Software Interface)

Stop

Stop condition as defined in I2C

Whenever writing to a subaddress, the correct number of data bytes must follow in order to complete the write cycle.

For example, if the volume control register with subaddress 04h is written to, six bytes of data must follow; otherwise,

the cycle will be incomplete and errors will occur.

3.2.2

I2C Timing and Wait Cycles

The TAS3001 issues I2C wait cycles to regulate the flow of command information. The TAS3001 can issue wait cycles

for each instruction. For any instruction, the TAS3001 can issue up to a one sample (23

µs) wait between data bytes

and between the last data byte and the I2C stop. This wait is generated after the acknowledgement. The duration of

this wait cycle is slightly longer than a sample interval, on the order of 1.1 x 1

÷ Fs ( or 25 µs at 44.1 kHz). This wait

cycle is illustrated in Figure 3−3.

Start

Slave Address

R/W

Subaddress

Data Byte 1

Wait

Data Byte 1

Wait

Data Byte 2

Wait

Data Byte N

Wait

Stop

Figure 3−3. Wait Cycle Example

The TAS3001 can also issue an I2C wait state after receiving an entire volume or tone command. The TAS3001

produces these wait cycles while it executes the interpolation algorithms from the present setting to the new setting.

The volume command always takes the same amount of time to process for a given sample rate. The treble and bass

commands vary depending upon the current index and the destination index. E.g., moving from −18 dB to 18 dB or

vice versa produces the longest wait.

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