TAS3001CPWR datasheet(18/56 Pages) TI

18 / 56 page

2−4

2.1.3

Right-Justified Serial Format

The following are characteristics of this protocol:

•

LRCLK is the left/right clock. The left channel is transmitted when LRCLK is high. The right channel is

transmitted when LRCLK is low.

•

The SDIN data (recorded data) is justified to the trailing edge of the LRCLK.

•

Serial data is sampled on the rising edge of SCLK.

•

Serial data is transmitted on the falling edge of SCLK.

•

In this mode, LRCLK does not have to be a 50% duty-cycle clock. The number of bits used in the interface

sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.

MSB

SDIN1

SCLK

MSB

LSB

MSB

LSB

Left Channel

Right Channel

SDOUT

LRCLK = fs

Figure 2−4. Right-Justified Serial Format

2.2

LRCLKOUT and SCLKOUT

The digital audio processor and on-chip logic are sequenced using an internal system clock that is derived from MCLK

(master clock). Also derived from MCLK are the LRCLKOUT and SCLKOUT signals that provide clocks to the

TAS3001 and other devices in the system.

The TAS3001 allows multiple system clocking schemes. In Figure 2−5, the TAS3001 provides system clocks (LRCLK

and SCLK) to other parts of the system. In Figure 2−6, a system master other than the TAS3001, provides system

clocks (LRCLK and SCLK) to the TAS3001.

TAS3001CPWR 数据表(PDF) 18 Page - Texas Instruments

TAS3001CPWR 数据表(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载