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3−3

However, this wait cycle does not occur during the volume or tone change command, instead it occurs during the next

command after the acknowledgement of the first data byte.

Table 3−4 gives typical values of the wait states of the TAS3001 commands.

Table 3−4. I2C Wait States

SYSTEM SAMPLING FREQUENCY

COMMENT

32 kHz

44.1 kHz

48 kHz

96 kHz

COMMENT

Volume

62 ms

49 ms

41 ms

21 ms

Not dependent on size of change

Bass

231 ms

167 ms

153 ms

77 ms

18 dB to −18 dB (proportional to step

change)

Treble

231 ms

167 ms

153 ms

77 ms

18 dB to −18 dB (proportional to step

change)

Mixer

None

Equalization

None

The I2C operation sequence that the TAS3001 uses to assert an I2C wait cycle is:

The TAS3001 detects a valid start condition and correct device ID. At this point the TAS3001 issues an ACK.

The TAS3001 decodes the eight-bit subaddress and issues another ACK.

The TAS3001 decodes the first data byte and issues a third ACK.

At this point, the TAS3001 device can hold the SCL clock line low until the internal controller is ready to

accept more data. This is an I2C slave wait state.

There are two ways a master can handle the I2C slave wait.

•

The preferred way to handle wait states is to use an I2C master that recognizes wait states. During the

wait-state period, the master stops sending data over I2C. In this case, when the master releases the clock

to go high after a slave ACK (to latch in the next bit of data), the master monitors the SCL line and ensures

that the slave has released SCL. Once SCL has been released the master can start the next transmission.

•

Alternatively, if this function is not available on the system controller, fixed delays can be implemented in

the system software to ensure that the TAS3001 is ready to receive additional data. Sending I2C data while

the TAS3002 device is busy causes errors and the device locks up and have to be reset.

Issuing a stop command in the middle of an I2C transaction puts the TAS3001 I2C slave block into an unknown state,

possibly locking up the controller or causing it to send incorrect data to the signal processing block.

3.2.3

Resetting the TAS3001 I2C Interface

To put the TAS3001 back into a known state, an I2C transaction with a subaddress of 00h and followed by 16 bytes

of zeros clears out the I2C slave block buffer. Resetting the device also puts it into a known state.

During normal operation, the TAS3001 should never issue a NACK. If the TAS3001 issues a NACK, this is an

indication of an I2C protocol discrepancy.

3.2.4

Power-Up Conditions

Upon system power up, the I2C bus SCL can initialize in a mode in which the line is held low. This prevents any I2C

operations from being performed. To prevent this from occurring, always hold RESET low for a minimum of 10 MCLK

clock cycles after applying power.

Upon reset, the TAS3001 goes through an initialization sequence with a duration of 5 ms.

Before a reset, the SDA and SCL lines may be held low by the device.

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