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ADAU1761BCPZ-R7 数据表(PDF) 44 Page - Analog Devices

部件名 ADAU1761BCPZ-R7
功能描述  24-Bit Audio Codec with Integrated PLL
PDF  93 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1761BCPZ-R7 数据表(HTML) 44 Page - Analog Devices

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ADAU1761
Rev. C | Page 43 of 92
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1/
fS
Figure 58. I2S Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1/
fS
Figure 59. Left-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1/
fS
Figure 60. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
SLOT 0
SLOT 3
SLOT 4
32 BCLKs
MSB
MSB – 1
MSB – 2
256 BCLKs
SLOT 1
SLOT 2
SLOT 5
SLOT 6
SLOT 7
LRCLK
BCLK
SDATA
Figure 61. TDM 8 Mode
LRCLK
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
CH
0
BCLK
SDATA
MSB TDM
CH
8
32
BCLKs
MSB TDM
Figure 62. TDM 8 Mode with Pulse Word Clock



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