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ADAU1761BCPZ-R7 数据表(PDF) 87 Page - Analog Devices

部件名 ADAU1761BCPZ-R7
功能描述  24-Bit Audio Codec with Integrated PLL
PDF  93 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1761BCPZ-R7 数据表(HTML) 87 Page - Analog Devices

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ADAU1761
Rev. C | Page 86 of 92
R65: Clock Enable 0, 16,633 (0x40F9)
This register disables or enables the digital clock engine for different blocks within the ADAU1761. For maximum power saving, use this
register to disable blocks that are not being used.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SLEWPD
ALCPD
DECPD
SOUTPD
INTPD
SINPD
SPPD
Table 90. Clock Enable 0 Register
Bits
Bit Name
Description
6
SLEWPD
Codec slew digital clock engine enable. When powered down, the analog playback path volume controls are
disabled and stay set to their current state.
0 = powered down (default).
1 = enabled.
5
ALCPD
ALC digital clock engine enable.
0 = powered down (default).
1 = enabled.
4
DECPD
Decimator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
3
SOUTPD
Serial routing outputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
2
INTPD
Interpolator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
1
SINPD
Serial routing inputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
0
SPPD
Serial port digital clock engine enable.
0 = powered down (default).
1 = enabled.
R66: Clock Enable 1, 16,634 (0x40FA)
This register enables Digital Clock Generator 0 and Digital Clock Generator 1. Digital Clock Generator 0 generates sample rates for the
ADCs, DACs, and DSP. Digital Clock Generator 1 generates BCLK and LRCLK for the serial port when the part is in master mode. For
maximum power saving, use this register to disable clocks that are not being used.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
CLK1
CLK0
Table 91. Clock Enable 1 Register
Bits
Bit Name
Description
1
CLK1
Digital Clock Generator 1.
0 = off (default).
1 = on.
0
CLK0
Digital Clock Generator 0.
0 = off (default).
1 = on.



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