ADAU1761BCPZ-R7 datasheet(81/93 Pages) AD

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ADAU1761

Rev. C | Page 80 of 92

R43 to R47: Cyclic Redundancy Check Registers, 16,576 to 16,580 (0x40C0 to 0x40C4)

The cyclic redundancy check (CRC) constantly checks the validity of the program RAM contents. SigmaStudio generates a 32-bit hash

sum, which must be written to four consecutive read-only 8-bit register locations. CRC must then be enabled. Every 1024 frames (21 ms

at 48 kHz), the IC generates its own 32-bit code and compares it to the one stored in these registers. If the codes do not match, a GPIO pin

is set high (CRC flag). This output flag must be enabled using the output CRC error sticky setting in the GPIO pin control register (see

Table 79). The 1-bit CRC error flag is reset when the CRCEN bit goes low. For example, a GPIO pin can be connected to an interrupt pin

on an external microcontroller, which triggers a rewrite of the corrupted memory.

By default, CRC is disabled (the CRCEN bit is set to 0). To enable continuous CRC checking, the user can set the CRCEN bit to 1 after

loading a program and sending the correct CRC, which is calculated by SigmaStudio. If an error occurs, it can be cleared by setting the

CRCEN bit low, fixing the error (presumably by reloading the program), and then setting the CRCEN bit high again.

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x40C0

CRC[31:24]

0x40C1

CRC[23:16]

0x40C2

CRC[15:8]

0x40C3

CRC[7:0]

0x40C4

Reserved

CRCEN

Table 78. Cyclic Redundancy Check Registers

Address

Decimal

Hex

Bit Name

Description

R43

16,576

0x40C0

CRC[31:24]

CRC hash sum, Bits[31:24] (read-only register)

R44

16,577

0x40C1

CRC[23:16]

CRC hash sum, Bits[23:16] (read-only register)

R45

16,578

0x40C2

CRC[15:8]

CRC hash sum, Bits[15:8] (read-only register)

R46

16,579

0x40C3

CRC[7:0]

CRC hash sum, Bits[7:0] (read-only register)

R47

16,580

0x40C4

CRCEN

CRC enable

0 = disabled (default)

1 = enabled

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