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ADAU1761BCPZ-R7 数据表(PDF) 77 Page - Analog Devices

部件名 ADAU1761BCPZ-R7
功能描述  24-Bit Audio Codec with Integrated PLL
PDF  93 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1761BCPZ-R7 数据表(HTML) 77 Page - Analog Devices

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ADAU1761
Rev. C | Page 76 of 92
R36: DAC Control 0, 16,426 (0x402A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DACMONO[1:0]
DACPOL
Reserved
DEMPH
DACEN[1:0]
Table 70. DAC Control 0 Register
Bits
Bit Name
Description
[7:6]
DACMONO[1:0]
DAC mono mode. The DAC channels can be set to mono mode within the DAC and output on the left
channel, the right channel, or both channels.
Setting
Mono Mode
00
Stereo (default)
01
Left channel in mono mode
10
Right channel in mono mode
11
Both channels in mono mode
5
DACPOL
Invert input polarity of the DACs.
0 = normal (default).
1 = inverted.
2
DEMPH
DAC de-emphasis filter enable. The de-emphasis filter is designed for use with a sampling rate of 44.1 kHz only.
0 = disabled (default).
1 = enabled.
[1:0]
DACEN[1:0]
DAC enable.
Setting
DACs Enabled
00
Both off (default)
01
Left on
10
Right on
11
Both on
R37: DAC Control 1, 16,427 (0x402B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDAVOL[7:0]
Table 71. DAC Control 1 Register
Bits
Bit Name
Description
[7:0]
LDAVOL[7:0]
Controls the digital volume attenuation for left channel inputs from the left DAC. Each bit corresponds to a
0.375 dB step with slewing between settings. See Table 94 for a complete list of the volume settings.
Setting
Volume Attenuation
00000000
0 dB (default)
00000001
−0.375 dB
00000010
−0.75 dB
11111110
−95.25 dB
11111111
−95.625 dB



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