ADAV801ASTZ datasheet(32/61 Pages) AD

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ADAV801

Rev. A | Page 31 of 60

SRC and Clock Control—Address 0000000 (0x00)

Table 17. SRC and Clock Control Register Bit Map

SRCDIV1

SRCDIV0

CLK2DIV1

CLK2DIV0

CLK1DIV1

CLK1DIV0

MCLKSEL1

MCLKSEL0

Table 18. SRC and Clock Control Register Bit Descriptions

Bit Name

Description

SRCDIV[1:0]

Divides the SRC master clock.

00 = SRC master clock is not divided.

01 = SRC master clock is divided by 1.5.

10 = SRC master clock is divided by 2.

11 = SRC master clock is divided by 3.

CLK2DIV[1:0]

Clock divider for Internal Clock 2 (ICLK2).

00 = Divide by 1.

01 = Divide by 1.5.

10 = Divide by 2.

11 = Divide by 3.

CLK1DIV[1:0]

Clock divider for Internal Clock 1 (ICLK1).

00 = Divide by 1.

01 = Divide by 1.5.

10 = Divide by 2.

11 = Divide by 3.

MCLKSEL[1:0]

Clock selection for the SRC master clock.

00 = Internal Clock 1.

01 = Internal Clock 2.

10 = PLL recovered clock (512 × fS).

11 = PLL recovered clock (256 × fS).

S/PDIF Loopback Control—Address 0000011 (0x03)

Table 19. S/PDIF Loopback Control Register Bit Map

Reserved

TxMUX

Table 20. S/PDIF Loopback Control Register Bit Descriptions

Bit Name

Description

TxMUX

Selects the source for S/PDIF output (DITOUT).

0 = S/PDIF transmitter, normal mode.

1 = DIRIN, loopback mode.

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