数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ADAV801ASTZ 数据表(PDF) 18 Page - Analog Devices

部件名 ADAV801ASTZ
功能描述  Audio Codec for Recordable DVD
PDF  61 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAV801ASTZ 数据表(HTML) 18 Page - Analog Devices

Back Button ADAV801ASTZ Datasheet HTML 14Page - Analog Devices ADAV801ASTZ Datasheet HTML 15Page - Analog Devices ADAV801ASTZ Datasheet HTML 16Page - Analog Devices ADAV801ASTZ Datasheet HTML 17Page - Analog Devices ADAV801ASTZ Datasheet HTML 18Page - Analog Devices ADAV801ASTZ Datasheet HTML 19Page - Analog Devices ADAV801ASTZ Datasheet HTML 20Page - Analog Devices ADAV801ASTZ Datasheet HTML 21Page - Analog Devices ADAV801ASTZ Datasheet HTML 22Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 61 page
background image
ADAV801
Rev. A | Page 17 of 60
Selecting a Sample Rate
The output sample rate of the ADC is always ADC MCLK/256,
as shown in Figure 23. By default, the ADC modulator runs at
ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz,
the ADC modulator should be set to run at ADC MCLK/4. This
is achieved by setting the AMC (ADC Modulator Clock) bit in
the ADC Control Register 1. To compensate for the reduced
modulator clock speed, a different set of filters are used in the
decimator section, ensuring that the sample rate remains
the same.
The AMC bit can also be used to boost the THD + N perform-
ance of the ADC at the expense of dynamic range. The
improvement is typically 0.5 dB to 1.0 dB and works because
selecting the lower modulator rate reduces the amount of digital
noise, improving THD + N, but also reduces the oversampling
ratio, therefore reducing the dynamic range by a corresponding
amount.
For best performance of the ADC, avoid using similar frequency
clocks from separate sources in the ADAV801. For example,
running the ADC from a 12.288 MHz clock connected to
MCLKI and using the PLL to generate a separate 12.288 MHz
clock for the DAC can reduce the performance of the ADC.
This is due to the interaction of the clocks, which generate beat
frequencies that can affect the charge on the switch capacitors of
the analog inputs.
WAIT FOR SAMPLE
WAIT FOR SAMPLE
WAIT FOR SAMPLE
DECREASE GAIN BY 0.5dB
AND WAIT ATTACK TIME
IS A RECOVERY
MODE ENABLED?
IS SAMPLE
GREATER THAN ATTACK
THRESHOLD?
IS SAMPLE
ABOVE ATTACK
THRESHOLD?
ARE ALL
SAMPLES BELOW
RECOVERY
THRESHOLD?
HAS GAIN BEEN
FULLY RESTORED?
YES
YES
YES
NO
YES
YES
NO
NO
NORMAL RECOVERY
INCREASE GAIN BY 0.5dB
WAIT RECOVERY TIME
LIMITED RECOVERY
ATTACK MODE
IS SAMPLE
ABOVE ATTACK
THRESHOLD?
ARE ALL
SAMPLES BELOW
RECOVERY
THRESHOLD?
HAS GAIN BEEN
FULLY RESTORED?
IS GAINCNTR
AT MAXIMUM?
YES
NO
NO
YES
YES
YES
NO
NO
INCREASE GAIN BY 0.5dB
NO
INCREMENT
GAINCNTR
NO
NO
NO
HAS RECOVERY
TIME BEEN
REACHED?
HAS RECOVERY
TIME BEEN
REACHED?
Figure 26. ALC Flow Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com