ADAV801ASTZ datasheet(23/61 Pages) AD

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ADAV801

Rev. A | Page 22 of 60

PLL SECTION

The ADAV801 features a dual PLL configuration to generate

independent system clocks for asynchronous operation.

Figure 37 shows the block diagram of the PLL section. The PLL

generates the internal and system clocks from a 27 MHz clock.

This clock is generated either by a crystal connected between

XIN and XOUT, as shown in Figure 35, or from an external

clock source connected directly to XIN. A 54 MHz clock can

also be used, if the internal clock divider is used.

XTAL

Figure 35. Crystal Connection

Both PLLs (PLL1 and PLL2) can be programmed independently

and can accommodate a range of sampling rates (32 kHz/

44.1 kHz/48 kHz) with selectable system clock oversampling

rates of 256 and 384. Higher oversampling rates can also be

selected by enabling the doubling of the sampling rate to give

512 or 768 × fS ratios. Note that this option also allows

oversampling ratios of 256 or 384 at double sample rates of

64 kHz/88.2 kHz/96 kHz.

The PLL outputs can be routed internally to act as clock sources

for the other component blocks such as the ADC and DAC. The

outputs of the PLLs are also available on the three SYSCLK pins.

Figure 38 shows how the PLLs can be configured to provide the

sampling clocks.

Table 7. PLL Frequency Selection Options

MCLK Selection

PLL

Sample Rate, fS

(kHz)

Normal fS

Double fS

32/44.1/48

256/384 × fS

512/768 × fS

64/88.2/96

256/384 × fS

32/44.1/48

256/384 × fS

512/768 × fS

64/88.2/96

256/384 × fS

Same as fS selected

256/512 × fS

for PLL2A

The PLLs require some external components to operate

correctly. These components, shown in Figure 36, form a loop

filter that integrates the current pulses from a charge pump and

produces a voltage that is used to tune the VCO. Good quality

capacitors, such as PPS film, are recommended. Figure 37

shows a block diagram of the PLL section, including the master

clock selection. Figure 38 shows how the clock frequencies at

the clock output pins, SYSCLK1 to SYSCLK3, and the internal

PLL clock values, PLL1 and PLL2, are selected.

The clock nodes, PLL1 and PLL2, can be used as master clocks

for the other blocks in the ADAV801, such as the DAC or ADC.

The PLL has separate supply and ground pins, which should be

as clean as possible to prevent electrical noise from being

converted into clock jitter by coupling onto the loop filter pins.

PLL BLOCK

PLL_LFx

732Ω

1.2µF

AVDD

10nF

Figure 36. PLL Loop Filter

MCLKI

MCLKO

XOUT

XIN

REG 0x74

BIT 5

REG 0x74

BIT 4

REG 0x78

BIT 6

REG 0x78

BIT 7

PHASE

DETECTOR

AND LOOP

FILTER

PLL_LF1

PLL1

SYSCLK1

SYSCLK2

SYSCLK3

PLL_LF2

÷2

VCO

÷N

OUTPUT

SCALER N1

PHASE

DETECTOR

AND LOOP

FILTER

PLL2

VCO

÷N

OUTPUT

SCALER N2

OUTPUT

SCALER N3

Figure 37. PLL Section Block Diagram

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