ADAV801ASTZ datasheet(53/61 Pages) AD

53 / 61 page

ADAV801

Rev. A | Page 52 of 60

PLL Control Register 1—Address 1110100 (0x74)

Table 128. PLL Control Register 1 Bit Map

DIRIN_CLK1

DIRIN_CLK0

MCLKODIV

PLLDIV

PLL2PD

PLL1PD

XTLPD

SYSCLK3

Table 129. PLL Control Register 1 Bit Descriptions

Bit Name

Description

DIRIN_CLK[1:0]

Recovered S/PDIF clock sent to SYSCLK3.

00 = SYSCLK3 comes from PLL block.

01 = Reserved.

10 = Reserved.

11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN.

MCLKODIV

Divide input MCLK by 2 to generate MCLKO.

0 = Disabled.

1 = Enabled.

PLLDIV

Divide XIN by 2 to generate the PLL master clock.

0 = Disabled.

1 = Enabled.

PLL2PD

Power-down PLL2.

0 = Normal.

1 = Power-down.

PLL1PD

Power-down PLL1.

0 = Normal.

1 = Power-down.

XTLPD

Power-down XTAL oscillator.

0 = Normal.

1 = Power-down.

SYSCLK3

Clock output for SYSCLK3.

0 = 512 × fS.

1 = 256 × fS.

ADAV801ASTZ 数据表(PDF) 53 Page - Analog Devices

ADAV801ASTZ 数据表(HTML) 53 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表下载

链接网址

ADAV801ASTZ 数据表(PDF) 53 Page - Analog Devices

ADAV801ASTZ 数据表(HTML) 53 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表 下载

链接网址

数据表下载