ADAV801ASTZ datasheet(55/61 Pages) AD

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ADAV801

Rev. A | Page 54 of 60

Internal Clocking Control Register 1—Address 1110110 (0x76)

Table 132. Internal Clocking Control Register 1 Bit Map

DCLK2

DCLK1

DCLK0

ACLK2

ACLK1

ACLK0

ICLK2_1

ICLK2_0

Table 133. Internal Clocking Control Register 1 Bit Descriptions

Bit Name

Description

DCLK[2:0]

DAC clock source select.

000 = XIN.

001 = MCLKI.

010 = PLLINT1.

011 = PLLINT2.

100 = DIR PLL (512 × fS).

101 = DIR PLL (256 × fS).

110 = XIN.

111 = XIN.

ACLK[2:0]

ADC clock source select.

000 = XIN.

001 = MCLKI.

010 = PLLINT1.

011 = PLLINT2.

100 = DIR PLL (512 × fS).

101 = DIR PLL (256 × fS).

110 = XIN.

111 = XIN.

ICLK2_[1:0]

Source selector for internal clock ICLK2.

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

Internal Clocking Control Register 2—Address 1110111 (0x77)

Table 134. Internal Clocking Control Register 2 Bit Map

Reserved

ICLK1_1

ICLK1_0

PLL2INT1

PLL2INT0

PLL1INT

Table 135. Internal Clocking Control Register 2 Bit Descriptions

Bit Name

Description

ICLK1_[1:0]

Source selector for internal clock ICLK1.

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

PLL2INT[1:0]

PLL2 internal selector (see Figure 38).

00 = FS2.

01 = FS2/2.

10 = FS3.

11 = FS3/2.

PLL1INT

PLL1 internal selector.

0 = FS1.

1 = FS1/2.

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