ADAV801ASTZ datasheet(56/61 Pages) AD

56 / 61 page

ADAV801

Rev. A | Page 55 of 60

PLL Clock Source Register—Address 1111000 (0x78)

Table 136. PLL Clock Source Register Bit Map

PLL2_Source

PLL1_Source

Reserved

Table 137. PLL Clock Source Register Bit Descriptions

Bit Name

Description

PLL2_Source

Selects the clock source for PLL2.

0 = XIN.

1 = MCLKI.

PLL1_Source

Selects the clock source for PLL1.

0 = XIN.

1 = MCLKI

PLL Output Enable—Address 1111010 (0x7A)

Table 138. PLL Output Enable Register Bit Map

Reserved

DIRINPD

DIRIN_PIN

Reserved

SYSCLK1

SYSCLK2

SYSCLK3

Table 139. PLL Output Enable Register Bit Descriptions

Bit Name

Description

DIRINPD

This bit powers down the S/PDIF receiver.

0 = Normal.

1 = Power-down.

DIRIN_PIN

This bit determines the input levels of the DIRIN pin.

0 = DIRIN accepts input signals down to 200 mV according to AES3 requirements.

1 = DIRIN accepts input signals as defined in the Specifications section.

SYSCLK1

Enables the SYSCLK1 output.

0 = Enabled.

1 = Disabled.

SYSCLK2

Enables the SYSCLK2 output.

0 = Enabled.

1 = Disabled.

SYSCLK3

Enables the SYSCLK3 output.

0 = Enabled.

1 = Disabled.

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