ADAV801ASTZ datasheet(21/61 Pages) AD

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ADAV801

Rev. A | Page 20 of 60

The worst-case images can be computed from the zero-order

hold frequency response:

Maximum Image = sin(π × F/fS_INTERP)/(π × F/fS_INTERP)

where:

F is the frequency of the worst-case image that would be

220 × fS_IN ± fS_IN/2.

fS_INTERP = fS_IN × 220.

The following worst-case images would appear for fS_IN equal to

192 kHz:

Image at fS_INTERP − 96 kHz = −125.1 dB

Image at fS_INTERP + 96 kHz = −125.1 dB

Hardware Model

The output rate of the low-pass filter in Figure 30 is the

interpolation rate:

220 × 192,000 kHz = 201.3 GHz

Sampling at a rate of 201.3 GHz is clearly impractical, in

addition to the number of taps required to calculate each

interpolated sample. However, because interpolation by 220

involves zero-stuffing 220 − 1 samples between each fS_IN sample,

most of the multiplies in the low-pass FIR filter are by zero. A

further reduction can be realized because only one interpolated

sample is taken at the output at the fS_OUT rate, so only one

convolution needs to be performed per fS_OUT period instead of

220 convolutions. A 64-tap FIR filter for each fS_OUT sample is

sufficient to suppress the images caused by the interpolation.

One difficulty with the preceding approach is that the correct

interpolated sample must be selected upon the arrival of fS_OUT.

Because there are 220 possible convolutions per fS_OUT period, the

arrival of the fS_OUT clock must be measured with an accuracy of

1/201.3 GHz = 4.96 ps. Measuring the fS_OUT period with a clock

of 201.3 GHz frequency is clearly impossible; instead, several

coarse measurements of the fS_OUT clock period are made and

averaged over time.

Another difficulty with the preceding approach is the number

of coefficients required. Because there are 220 possible convolu-

tions with a 64-tap FIR filter, there must be 220 polyphase

coefficients for each tap, which requires a total of 226 coeffi-

cients. To reduce the number of coefficients in ROM, the SRC

stores a small subset of coefficients and performs a high order

interpolation between the stored coefficients.

The preceding approach works when fS_OUT > fS_IN. However,

when the output sample rate, fS_OUT, is less than the input sample

rate, fS_IN, the ROM starting address, input data, and length of

the convolution must be scaled. As the input sample rate rises

over the output sample rate, the antialiasing filter’s cutoff

frequency must be lowered because the Nyquist frequency of

the output samples is less than the Nyquist frequency of the

input samples. To move the cutoff frequency of the antialiasing

filter, the coefficients are dynamically altered and the length of

the convolution is increased by a factor of (fS_IN/fS_OUT).

This technique is supported by the Fourier transform property

that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of

decimation is limited by the size of the RAM.

SRC Architecture

The architecture of the sample rate converter is shown in

Figure 32. The sample rate converter’s FIFO block adjusts the

left and right input samples and stores them for the FIR filter’s

convolution cycle. The fS_IN counter provides the write address

to the FIFO block and the ramp input to the digital servo loop.

The ROM stores the coefficients for the FIR filter convolution

and performs a high order interpolation between the stored

coefficients. The sample rate ratio block measures the sample

rate for dynamically altering the ROM coefficients and scaling

of the FIR filter length as well as the input data. The digital

servo loop automatically tracks the fS_IN and fS_OUT sample rates

and provides the RAM and ROM start addresses for the start of

the FIR filter convolution.

RIGHT DATA IN

LEFT DATA IN

FIFO

DIGITAL

SERVO LOOP

fS_IN

COUNTER

ROM A

ROM B

ROM C

ROM D

fS_IN

fS_OUT

SAMPLE RATE RATIO

SAMPLE

RATE RATIO

EXTERNAL

RATIO

HIGH

ORDER

INTERP

FIR FILTER

L/R DATA OUT

Figure 32. Architecture of the Sample Rate Converter

The FIFO receives the left and right input data and adjusts the

amplitude of the data for both the soft muting of the sample rate

converter and the scaling of the input data by the sample rate

ratio before storing the samples in the RAM. The input data is

scaled by the sample rate ratio because, as the FIR filter length

of the convolution increases, so does the amplitude of the

convolution output. To keep the output of the FIR filter from

saturating, the input data is scaled down by multiplying it by

(fS_OUT/fS_IN) when fS_OUT < fS_IN. The FIFO also scales the input

data for muting and unmuting of the SRC.

The RAM in the FIFO is 512 words deep for both left and right

channels. An offset to the write address provided by the fS_IN

counter is added to prevent the RAM read pointer from

overlapping the write address. The minimum offset on the SRC

is 16 samples. However, the group delay and mute-in register

can be used to increase this offset.

The number of input samples added to the write pointer of the

FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay

prevent the read pointer to the FIFO from running ahead of the

write pointer. When set, Bit 7 of the group delay and mute-in

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