L9679P datasheet(180/272 Pages) STMICROELECTRONICS

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Watchdog timers

L9679P

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DocID029275 Rev 1

Watchdog timers

This device offers a 2-level watchdog control approach. The first control level is given by

means of a temporal watchdog (WD1). The WD1 window times are SPI programmable and

a couple of specific codes have to be written within this window in order to serve the WD1

control. The second control level is featured by an algorithmic seed/key watchdog (WD2).

Unlike the temporal watchdog, the algorithmic watchdog service must be maintained before

a timeout occurs, i.e. there is no restriction on refreshing the watchdog too early. Both WD1

and WD2 watchdog functionalities can be tested trough the WD_TEST SPI command.

10.1

Temporal watchdog (WD1)

The temporal watchdog ensures the system software is operating correctly by requiring

periodic service from the microcontroller at a programmable rate. This service (watchdog

refresh) must occur within a time window, and if serviced too early or too late will enter an

error state reported via the FLTSR register (WD1_WDR bit).

The overall WD1 functionality is described in the state diagram reported in Figure 44.

Figure 44. WD1 Temporal watchdog state diagram

Following the description of the WD1 states and signals (most of them reported in related

SPI registers)

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