ATPL230A datasheet(12/122 Pages) ATMEL

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ATPL230A [DATASHEET]

Atmel-43053J-ATPL230A-Datasheet_22-Sep-16

SPI Controller

ATPL230A has been conceived to be easily managed by an external microcontroller through a 5-line interface. This

interface is comprised of a 4-line standard Serial Peripheral Interface (SPI) and an additional line used as interrupt

from the ATPL230A to the external microcontroller. A diagram is shown below.

Figure 6-1.

SPI Controller Block Diagram

By means of this SPI interface, an external microcontroller can access the ATPL230A and can carry out “write”,

“write_rep”, “read” and “mask” operations. All the “Peripheral Registers” in ATPL230A are reachable via the SPI

interface, thus the microcontroller can fully manage and control the ATPL230A (PHY layer, MAC co-processing, etc).

6.1

Serial Peripheral Interface

The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard. Devices communicate in

master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual

slave select (chip select) lines.

Figure 6-2.

SPI Communication Example in ATPL230A

SPI

Bridge

ATPL230A

SCK

MOSI

MISO

EINT

Microcontroller

Interrupt

Serial

Peripheral

Interface

5-line

Interface

to/from

microcontroller

MISO (READ_EXAMP LE)

SPI_INACTIVE

SPI_ACTIVE

SPI_CLK

MOSI

OPCODE (7

….0)

A DDRESS (15

….0)

BYTE DUMMY (7

….0)

/SS

A14

A15

D1 D0

DUMMY 7

….DUMMY0

….

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