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ATPL230A 数据表(PDF) 40 Page - ATMEL Corporation |
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ATPL230A 数据表(HTML) 40 Page - ATMEL Corporation |
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40 / 122 page  ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 40 8.3.1.13 Peripheral CRC Control Register Name: VCRC_CTL Address: 0xFF18 Access: Read/Write Reset: 0x00 The VCRC_CTL register contains the following control bits: • BUSY: ‘0’: VCRC block is ready to receive a new data byte. ‘1’: VCRC block is busy performing calculations. Unable to write in VCRC_INPUT register. • RESTART: Configures desired circuit feedback type: ‘0’: Reset disable. After a reset, RESTART bit is set to ‘0’ automatically after a period of time. ‘1’: Reset enable. Delete the actual VCRC_CRC register value and does not affect configuration registers. 76543210 0 0 0 BUSY 0 0 0 RESTART |
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