ATPL230A datasheet(13/122 Pages) ATMEL

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ATPL230A [DATASHEET]

Atmel-43053J-ATPL230A-Datasheet_22-Sep-16

The ATPL230A SPI allows an external device (working as a master), to communicate with the ATPL230A (working as

a slave). Below is a brief description of the SPI signals:



CS, Chip Select (pin no.24):

This input enables/disables the slave SPI. The ATPL230A is configured to work

always as a slave. When disabled (CS pin is tied high), the other SPI signals (SCK, MOSI and MISO) are not

taken into account.

CS = ‘0’: SPI enabled.

CS = ‘1’: SPI disabled.



SCK, Serial Peripheral Interface Clock (pin no.25):

In reception (master slave), data is read from MOSI line

in the rising edge of the SPI clock. In transmission (slave master), data is released to MISO in the falling edge

of the SPI clock.

It is recommended not to work with clock frequencies above 10MHz.

This input only will be taken into account when CS=’0’.



MOSI, Master Out Slave In (pin no.26):

MOSI is the slave’s data input line. Data is read from MOSI line in the

rising edge of SCK.

This input only will be taken into account when CS=’0’.



MISO, Master In Slave Out (pin no.27):

MISO is the slave’s data output line. Data is released to MISO in the

falling edge of SCK.

Furthermore, ATPL230A SPI bridge uses an additional line to send interrupts to the host CPU:



EINT (pin no.60):

This signal is an interrupt from ATPL230A PHY layer to the microcontroller.

In reception, every time a PLC message is received, the PHY Layer generates two interrupts. One of them

when the physical header is correctly received (two first symbols), and the other one when the message is

completely received.

In transmission, an interrupt will be generated every time a complete message has been sent.

This signal is low level active.

6.2

SPI Operation

When establishing a SPI communication (CS line is set to ‘0’ by the master), the first byte sent through MOSI line

corresponds to the operation code. Four different operation types are defined over ATPL230A SPI. The operation

codes are shown in the following table:

Following the operation code, the second and third bytes correspond to the SRAM address (16-bit address).

Depending on the operation code, the master will “read data from”/”write data to”/”mask data in”/”write some data to”

that address.

After the address, a dummy byte is sent.

Table 6-1.

Operation Codes

Operation

Mask type

OpCode

Read

---

0x63

Write

---

0x2A

Mask

AND

0x4C

0x71

XOR

0x6D

Write_rep

---

0x1E

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