ATPL230A datasheet(5/122 Pages) ATMEL

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ATPL230A [DATASHEET]

Atmel-43053J-ATPL230A-Datasheet_22-Sep-16

Notes: 1. Separate pins are provided for GND and AGND grounds. Layout considerations should be taken into account to

reduce interference. Ground pins should be connected as shortly as possible to the system ground plane. For

more details about EMC Considerations, please refer to AVR040 application note.

2. The crystal should be located as close as possible to CLKEA and CLKEB pins. See Table 10-7 on page 112.

3. See Table 10-5 on page 109.

4. Different configurations allowed depending on external topology and net behavior.

5. Depending on whether an isolated or a non-isolated power supply is being used, isolation of this pin should be

taken into account in the circuitry design. Please refer to the Reference Design for further information.

TXRX0

Analog Front-End Transmission/Reception for

TXDRV0

• This digital output is used to modify

external

coupling

behavior

Transmission/Reception.

The

suitable

value depends on the external circuitry

configuration. The polarity of this pin can be

inverted by software.

Output

VDDIO

TXRX1

Analog Front-End Transmission/Reception for

TXDRV1

• This digital output is used to modify

external

coupling

behavior

Transmission/Reception.

The

suitable

value depends on the external circuitry

configuration. The polarity of this pin can be

inverted by software.

Output

VDDIO

VZ CROSS(5)

Mains Zero-Cross Detection Signal:

• This input detects the zero-crossing of the

mains voltage

Input

VDDIO

Internal pull down(3)

VIMA

Negative Differential Voltage Input

Input

VDDOUT AN

VIPA

Positive Differential Voltage Input

Input

VDDOUT AN

VRP

Internal Reference “Plus” Voltage. Connect an

external decoupling capacitor between VRP

and VRM (1nF - 100nF)

Output

VDDOUT AN

VRM

Internal Reference “Minus” Voltage. Connect

an external decoupling capacitor between

VRP and VRM (1nF - 100nF)

Output

VDDOUT AN

VRC

Common-mode Voltage. Bypass to analog

ground with an external decoupling capacitor

(100pF - 1nF)

Output

VDDOUT AN

Serial Peripheral Interface - SPI

SPI CS

• SPI bridge Slave Select

Input

Low

VDDIO

Internal pull up(3)

SCK

SPI SCK

• SPI bridge Clock signal

Input

VDDIO

Internal pull up(3)

MOSI

SPI MOSI

• SPI bridge Master Out Slave In

Input

VDDIO

Internal pull up(3)

MISO

SPI MISO

• SPI bridge Master In Slave Out

Output

VDDIO

EINT

PHY Layer External Interrupt

Output

Low

VDDIO

Table 3-1.

Signal Description List

Signal Name

Function

Type

Active

Level

Voltage

reference

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