NCV7728

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13

OPERATING DESCRIPTION

General Overview

The NCV7728 is comprised of twelve DMOS power

drivers (six PMOS High Side Driver and six NMOS Low

Side Driver) configured as six half bridges that enables three

independent Full Bridge operations. Each output drive is

characterized for a max 550 mA DC load and has a typical

2 A surge capability (at VSx =13.2 V). Strict adherence to

integrated circuit die temperature is necessary. Maximum

die temperature is 150

°C. This may limit the number of

drivers enabled at one time. Output drive control and fault

reporting is handled via the SPI (Serial Peripheral Interface)

port.

An Enable function (EN) provides a low quiescent sleep

current mode when the device is not being utilized. No data

is stored when the device is in sleep mode. An internal pull

down resistor is provided on the EN input to ensure the

device is off if the input signal is lost. De−asserting the EN

signal clears all the registers and resets the driver. When the

cycle and brings the drivers into normal operation.

SPI Communication

16−bit full duplex SPI communication has been

implemented for the communication of this IC for device

configurations, driver controls and reading the diagnostic

data. In addition to the 16−bit diagnostic data, a pseudo bit

(PRE_15) can also be retrieved from the SO register. The

part is required to be enabled (EN active high) for SPI

communication. The inputs for the SPI are TTL logic

compatible and are specified by the VthInH and VthInL

thresholds. The active low CSB input has a pull up resistor

and the remaining SPI inputs have pull−down resistors to

bias them to a known state when SPI is not active.

Reference the SPI communication frame format diagram

in Figure 13 for the 16 bit SPI implementation. Tables 1

and 2 define the programming bits and diagnostic bits

shown in Figure 13.

SPI COMMUNICATION FRAME FORMAT

Figure 13. SPI Communication Frame Format

CSB

SI

SO

SCLK

SSR

HBSEL

PSF

HBCNF6 – HBCNF1

OVLO

TW

HBEN6 – HBEN1

ULD

0

14

13

15

OCS

ULD

HBx[1:0]

TSD

Communication is implemented as follows and is also illustrated in Figure 17:

1. SI and SCLK are set to low before the CSB cycle.

2. CSB goes low to allow serial data transfer.

3. SI data starting with the Most Significant bit (MSB) is shifted in first.

4. SI data is recognized on every falling edge of the clock.

5. Simultaneously, SO data from the previous frame starting with the MSB bit is shifted out on every rising edge of the

clock.

6. The input data is compared to a 16 bit counter for the initial 16 bits shifted into SI for frame detection error scheme.

7. The sequential input bits are compared to a n x 8 (n can take on the value of any integer) bit counter for daisy chain

operations and are monitored by the frame detection error scheme.

8. CSB goes high and the most recent 16 bits clocked into SI are transferred to the data register given that there is no

frame detection error. Otherwise the entire frame is ignored.

9. SO is tri−state when CSB is high.