NCV7728

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22

Over Current Detection and Shutdown

The NCV7728 offers over current shutdown protection on

the OUTx pins by monitoring the current on the high side

and low side drivers. If the over current threshold is

breached, the corresponding output is latched off (HS and

LS driver is latched off) after the specified shutdown time,

TdOc. Upon over current shutdown, the serial output bit

OCS will be set and the corresponding HBx[1:0] will be

changed to “01” to denote a high power dissipation state.

Devices can be turned back on via the SPI port once the OCS

condition is cleared by setting the SRR to ‘1’ on the next SPI

command. The event triggering the over current shutdown

condition must be resolved prior to clearing the OCS bit to

avoid repetitive stress on the drivers. Failure to do so may

result in non reversible fatal damage.

The SO data OCS shown on Figure 23 corresponds to both

the global SO bit #15 and the HBx OCS encoding state ‘01’.

Note: high currents could cause a high rise in die

temperature. Devices will turn off if the die temperature

exceeds the thermal shutdown temperature.

Figure 23. Over−Current Timing Diagram

OUTx

ON

OCS

IsdSxx

t

SI

Status

Output

State

SO

OUTx ON

SRR=0

OUTx

ON

No

Fault

OUTx ON

SRR=1

OUTx

ON

OUTx Z

Output

Current

OUTx

ON

No

Fault

No

Fault

TdOc

OCS

OUTx Z

TdOc

OUTx

ON

No

Fault

No

Fault

OUTx

ON

OCS

OCS

OCS

Under Load Detection

The under−load detection is employed on both the HS and

LS drivers. A global output bit (ULD) reports under load

fault if at least one of the channels detect an under load

condition. When configured for either LS or HS operation,

a minimum load current (IuldLS or |IuldHS| − this is the

maximum open circuit detection threshold) is required when

the drivers are turned on to avoid an under−load condition.

If the under−load detection threshold has been breached

longer than the specified under−load timer (TdUld), the

ULD output bit is set to ‘1’ and HBx[1:0] bits transitions to

“10”. Furthermore, if the Under−Load Detection Shutdown

Control (ULDSC bit # 13) input bit is set then the offending

half−bridge output will be turned off (HS and LS drivers will

be latched off). Otherwise the outputs remain active and the

device configuration can be changed. The SO reporting is

stored until the SRR clears the fault. Since an OCS fault has

a higher priority over an under load fault, the HBx[1:0]

under load fault state can be masked by an over current fault.

There is only one global under load timer for all the

drivers. If the TdUld timer is already activated due to one

under load, any subsequent under load delays will be the

remainder of the TdUld timer.

Table 4. UNDER−LOAD DRIVER STATUS

ULDSC Input

Bit 13

OUTx ULD

Condition

Output Data Bit Under Load Detect Sta-

tus

OUTx Status

0

0

‘0’

Unchanged

0

1

‘1’

(Need SRR to reset)

Unchanged

1

0

‘0’

Unchanged

1

1

‘1’ (Need SRR to reset)

OUTx Latches off (Need SRR to reset)

The ULD SO data provided in the under load timing diagram in Figure 24 reflects the global ULD SO bit #13 and the HBx

ULD encoding state ‘10’.