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NCV7728DPAR2G 数据表(PDF) 23 Page - ON Semiconductor |
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NCV7728DPAR2G 数据表(HTML) 23 Page - ON Semiconductor |
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23 / 27 page ![]() NCV7728 www.onsemi.com 23 SI Status Output State SO Output Current t LSx ON ULDSC=0 LSx ON No Fault LSx ON SRR=1 No Fault No Fault ULD OUTx ON No Fault ULD ULD LSx ON ULDSC=1 ULD LSx ON SRR=1 LSx ON ULD OUTx GND IuldLS TdUld TdUld OUTx Z OUTx GND No Fault No Fault TdUld TdUld OUTx VS HSx ON ULDSC=0 No Fault HSx ON SRR=1 ULD ULD HSx ON ULDSC=1 OUTx Z IuldHS 0A ULD No Fault TdUld Figure 24. LS Under−load Timing Diagram Thermal Warning and Thermal Shutdown The NCV7728 provides individual thermal sensors for each half−bridge. Moreover, the sensor reports over temperature warning level and an over temperature shutdown level. The TW status bit (output bit 0) will be set if the temperature exceeds the over temperature warning level, but the drivers will remain active. Once the IC temperature fall below the thermal warning threshold the TW flag is automatically clearly. If any of the individual thermal sensors detects a thermal shutdown level then the drivers on the offending half bridge are latched off. The TSD (PRE_15) bit is set to capture a thermal shutdown event. A valid SPI command with SRR and temperature below the Tsd threshold are required to clear the latched fault. Since thermal warning precedes an over temperature shutdown, software polling of this bit will allow load control and possible prevention of over temperature shutdown conditions. Figure 25. Thermal Warning and Shutdown Timing Diagram OUTx ON t SI Status Output State SO OUTx ON No Fault TSD TWR TJ TW No Fault TW OUTx ON No Fault No Fault OUTx ON TW OUTx ON TW OUTx Z TwHy TsdHy OUTx ON SRR =1 TSD TW TSD TW TW OUTx ON SRR =1 TW OUTx ON TW |
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