SSM3515CCBZ-R7 datasheet(28/41 Pages) AD

28 / 41 page

SSM3515

Data Sheet

Rev. A| Page 28 of 41

LAYOUT

As output power increases, care must be taken to lay out PCB

traces and wires properly among the amplifier, load, and power

supply; a poor layout increases voltage drops, consequently

decreasing efficiency. A good practice is to use short, wide PCB

tracks to decrease voltage drops and minimize inductance. For

lowest dc resistance (DCR) and minimum inductance, ensure

that track widths are at least 200 mil for every inch of length

and use 1 oz or 2 oz copper. Use large traces for the power supply

inputs and amplifier outputs. Proper grounding guidelines

improve audio performance, minimize crosstalk between

channels, and prevent switching noise from coupling into the

audio signal.

To maintain high output swing and high peak output power, the

PCB traces that connect the output pins to the load and supply

pins must be as wide as possible to maintain the minimum trace

resistances. It is also recommended that a large ground plane be

used for minimum impedances. In addition, good PCB layout

isolates critical analog paths from sources of high interference.

Separate high frequency circuits (analog and digital) from low

frequency circuits.

Properly designed multilayer PCBs can reduce EMI emission

and increase immunity to the RF field by a factor of 10 or more,

compared with double-sided boards. A multilayer board allows

a complete layer to be used for the ground plane, whereas the

ground plane side of a double-sided board is often disrupted by

signal crossover.

If the system has separate analog and digital ground and power

planes, the analog ground plane must be directly beneath the

analog power plane, and, similarly,the digital ground plane must

be directly beneath the digital power plane. There must be no

overlap between analog and digital ground planes or between

analog and digital power planes.

BOOTSTRAP CAPACITORS

The output stage of the SSM3515uses a high-side NMOSdriver,

rather than PMOS. Therefore, a bootstrap supply is needed to

drive the high-side NMOS. To generate the boosted gate driver

voltage for the high-side NMOS, a 0.22 μF bootstrap capacitor is

used from each output pinto BST± pins. This capacitor boosts the

voltage at BST± pins when the high-side NMOS turns on and

acts as a floating power supply for that particular switching

cycle. The bootstrap capacitor is charged during the low-side

NMOS active period.

POWER SUPPLYDECOUPLING

To ensure high efficiency, low total harmonic distortion (THD),

and high power supply rejection ratio (PSRR), proper power

supply decoupling is necessary. Noise transients on the power

supply lines are short duration voltage spikes. These spikes can

contain frequency components that extend into the hundreds of

megahertz. The power supply input must be decoupled with a

good quality, low ESL, low ESR bulk capacitor larger than

220 µF. This capacitor bypasses low frequency noises to the

ground plane.

For high frequency transient noises, place 1 µF capacitors as

close as possible to the PVDD pins of the device.

SSM3515CCBZ-R7 数据表(PDF) 28 Page - Analog Devices

SSM3515CCBZ-R7 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载