SSM3515CCBZ-R7 datasheet(24/41 Pages) AD

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SSM3515

Data Sheet

Rev. A| Page 24 of 41

ANALOG AND DIGITAL GAIN

Several selectable settings are available for the analog gain of the

system. These provide optimal gain settings at various PVDD supply

voltages. The ANA_GAIN bits are available in Register 0x01,

Bits[1:0].

The available options are as shown in Table 16.

Table 16. Analog Gain Options

PVDD

ANA_GAIN

Amplifier Analog Gain

Selection

5 V to 9 V

8.4 V full-scale gain mapping

9 V to 13 V

12.6 V full-scale gain mapping

13 V to 14 V

14 V full-scale gain mapping

14 V to 16 V

15 V full-scale gain mapping

There is also a digital gain or volume control that provides fine

control in 0.375 dB steps from −70 dB to +24 dB.

POP AND CLICK SUPPRESSION

Voltage transients at the output of audio amplifiers may occur

when shutdown is activated or deactivated. Voltage transients

as small as 10 mV can be heard as an audible pop in the speaker.

Clicks and pops are defined as undesirable audible transients

generated by the amplifier system that do not come from the

system input signal.

Such transients may be generated when the amplifier system

changes its operating mode. For example, system power-up and

power-down can be sources of audible transients.

The SSM3515 has a pop and click suppression architecture that

reduces these output transients, resulting in noiseless activation and

deactivation.

Either mute or power-down must be set before the BCLK is

removed to ensure a pop free power-down.

EMI NOISE

The SSM3515 uses a proprietary modulation and spread

spectrum technology to minimize EMI emissions from the

device. The SSM3515 can pass FCC Class B emissions testing

with an unshielded 20-inch cable using ferrite bead-based

filtering. For applications that have difficulty passing FCC Class B

emission tests, the SSM3515 includes a modulation select pin

(ultralow EMI emission mode) that significantly reduces the

radiated emissions at the Class-D outputs, particularly above

100 MHz. Note that reducing the supply voltage greatly reduces

radiated emissions.

OUTPUT MODULATION DESCRIPTION

The SSM3515 uses three-level, Σ-Δ output modulation. Each

output can swing from GND to PVDD and vice versa. Ideally, when

no input signal is present, the output differential voltage is 0 V

because there is no need to generate a pulse. In a real-world

situation, there are always noise sources present.

Due to this constant presence of noise, a differential pulse is

occasionally generated in response to this stimulus. A small

amount of current flows into the inductive load when the

differential pulse is generated. However, most of the time, the

output differential voltage is 0 V. This feature ensures that the

current flowing through the inductive load is small.

When the user sends an input signal, an output pulse is generated

to follow the input voltage. The differential pulse density is

increased by raising the input signal level. Figure 66 depicts

three-level, Σ-Δ output modulation with and without input

stimulus.

OUTPUT > 0V

+5V

OUT+

+5V

OUT–

+5V

VOUT

OUTPUT < 0V

+5V

OUT+

+5V

OUT–

–5V

NOTES

1. VOUT = (OUT+) – (OUT−) MEASURED ACROSS THE LOAD.

OUTPUT = 0V

OUT+

+5V

OUT–

+5V

–5V

VOUT

Figure 66. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus

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