SSM3515

Data Sheet

Rev. A| Page 2 of 41

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

General Description ......................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

Revision History ............................................................................... 2

 

Specifications..................................................................................... 3

 

Digital Timing Characteristics ................................................... 6

 

Absolute Maximum Ratings............................................................ 8

 

Thermal Resistance ...................................................................... 8

 

ESD Caution.................................................................................. 8

 

Pin Configuration and Function Descriptions............................. 9

 

Typical Performance Characteristics ........................................... 10

 

Theory of Operation ...................................................................... 19

 

Overview...................................................................................... 19

 

Power Supplies ............................................................................ 19

 

Power-Up Sequence ................................................................... 19

 

Power-Down Operation ............................................................ 19

 

REG_EN Pin Setup and Control .............................................. 19

 

ADDR Pin Setup and Control .................................................. 20

 

Clocking....................................................................................... 20

 

Digital Audio Serial Interface ....................................................... 21

 

Stereo (I2S/Left Justified) Operating Mode............................. 21

 

TDM Operating Mode............................................................... 21

 

I2C Control .................................................................................. 21

 

Analog and Digital Gain............................................................ 24

 

Pop and Click Suppression........................................................ 24

 

EMI Noise.................................................................................... 24

 

Output Modulation Description .............................................. 24

 

Faults and Limiter Status Reporting ........................................ 25

 

VBAT Sensing............................................................................. 25

 

Limiter and Battery Tracking Threshold Control.................. 25

 

Layout .......................................................................................... 28

 

Bootstrap Capacitors.................................................................. 28

 

Power Supply Decoupling ......................................................... 28

 

Register Summary .......................................................................... 29

 

Register Details ............................................................................... 30

 

Power Control Register ............................................................. 30

 

Gain and Edge Control Register............................................... 30

 

DAC Control Register................................................................ 31

 

DAC Volume Control Register................................................. 32

 

SAI Control 1 Register............................................................... 33

 

SAI Control 2 Register............................................................... 34

 

Battery Voltage Output Register............................................... 35

 

Limiter Control 1 Register ........................................................ 35

 

Limiter Control 2 Register ........................................................ 36

 

Limiter Control 3 Register ........................................................ 37

 

Status Register............................................................................. 37

 

Fault Control Register................................................................ 38

 

Typical Application Circuit ........................................................... 40

 

Outline Dimensions ....................................................................... 41

 

Ordering Guide .......................................................................... 41

 

REVISION HISTORY

1/2017—Rev. 0 to Rev. A

Changes to Figure 2 and Table 5..................................................... 6

6/2015—Revision 0: Initial Version